1. Technical Field
The present invention relates to a resistance switching memory.
2. Description of Related Art
It is highly desirable to develop a high-speed, low-power random access memory technology that is able to retain data under significant stress (e.g. 100° C. 10 years) and also simple to fabricate. Resistive random access memory (RRAM) currently is the strongest candidate to satisfy these criteria. While the technology is relatively forgiving in terms of structural requirements, certain processes in the fabrication sequence, e.g., etching, are more likely to damage the oxide, making its performance less attractive. Also, to enable scaling to smaller sizes, layouts are often preferred to be “lithography-friendly,” often suggesting the need to accommodate line-shaped structures and self-aligned contacts. Finally, the switching area is preferred to be confined to a sublithographic area.
In the related arts, Tseng patent (Vanguard, U.S. Pat. No. 5,744,387) disclosed a method of DRAM fabrication, where the bit line was patterned first and insulated by sidewall spacers before forming the capacitor. Huang patent (TSMC, U.S. Pat. Pub. No. 20010000242) disclosed a similar method of DRAM fabrication, except sidewall spacers were not formed, but the bit lines were still insulated and openings are etched through the insulating layer for the capacitor node contacts. Tu et al. (TSMC, U.S. Pat. Pub. No. 20060017115) disclosed fabricating an MIM capacitor with same process as for a metal gate electrode. The MIM capacitor has a top electrode overlying the capacitor dielectric.
Seo et al. (Samsung, U.S. Pat. Pub. No. 20080121864) disclosed a resistive random access memory and method of manufacturing the same. A stacked structure with two electrodes and a resistive layer including transition metal dopants interposed therein is disclosed. Choi et al. (Samsung, U.S. Pat. Pub. No. 20080170427) disclosed resistive random access memory devices including sidewall resistive layers and related methods. Both disclosed inventions suffer from potential processing damage during the etching of the resistance layer stack.